Three times DDR2 from 800 up to 1066 MHz. Corsair and OCZ
Introduction
After tours in the extreme fields beyond the 1100 MHz effective memory clock in the form of the Corsair Dominator series we devote ourselves today of again rather ordinary food. Although this report is again only modules of from well-known manufacturers, however in “traditional” clock regions from 800 up to 1066 MHz.
The products TWIN2X2048-6400 and TWIN2X1024-8500, Corsair provides two pairs of module while OCZ has sent the PC2-8000 Platinum extreme Edition XTC in the race.
Bookmark
As himself in the course of time a lot of articles on memory have accumulated, we want to once again these to remind. Because it sometimes happens that in today’s article on existing knowledge from older tests of memory modules is used, it is for those who want to know something “more”, certainly not wrong to take also a look at our older reports.
- 1111 MHz: Corsair XMS2 Dominator
- RAM: Intervals or timings?
- DDR1 vs. DDR2
- What bring 2 GB RAM?
- DDR2 – the basics
The test conditions
- Processor
- Intel Core 2 Extreme X 6800
- CPU cooler
- Intel boxed
- Motherboard
- ASUS P5B Deluxe WiFi-AP Edition
- BIOS: 0711 BETA
- Graphics card
- ATi Radeon X 1800 XL (500 / 500)
- Hard drive
- Samsung S-ATA 2-HDD 200 GB disk space (NCQ enabled)
- Power supply
- Corsair HX620W, 620 Watts
- Driver versions
- ATi catalyst 6.8
- Software
- Microsoft Windows XP Professional SP2
- Microsoft DirectX 9.0 c
- ClockGen 1.0.4.8
- MemSet 3.0
- MemTest 3.5
- Benchmarks
- 7-Zip 4.42
- SiSoft Sandra 2007 professional business SP1
- ScienceMark 2.0
So we test
Our focus in this article is at the maximum attainable clock rates and timings at as low memory voltage. The benchmark course is therefore limited to some a few applications, which are mainly theoretical. All benchmarks with possible high frontside bus were carried out to keep as small as possible the effect of the bottleneck between CPU and Northbridge. Because all current motherboards for AMD and Intel processors without DDR2-800 overclocking support, we have decided also, to test the memory at clock rates below effective 800 MHz.
The setting of the memory clock of the BIOS is relatively loosely possible and takes more time, so that we at the testing of maximum memory clock ClockGen to the vary the FSB clock used. We put to three flawless runs two parallel instances of MemTest stability criterion. A wholly owned stability is this although not guaranteed, experience has shown that working configurations that remain healthy, but also otherwise stable.
BIOS settings:
- PCI Express frequency: 100 MHz
- PCI clock synchronization mode: 33.33 MHz
- Spread spectrum: Disabled
- CPU VCore voltage: 1,425V
- FSB termination voltage: 1,45V
- NB VCore: 1,65V
- C1E support: Disabled
- Max CPUID value limit: Disabled
- Vanderpool technology: Disabled
- CPU TM function: disabled
- Execute Disable bit: disabled
- Modify ratio support: enabled
- Memory remap feature: Disabled
- Static read control: Disabled
The candidates
Corsair DDR2-800
At the default speed of effectively 800 MHz with timings of 5-5-5-12 (CAS, tRCD, tRP, tRAS) and 1,9V – in view of the 2 given, for example, when Corsairs Dominator modules (computer base test) from the factory some Dominator variants of Corsair gratifyingly low – voltage among the best representatives in the DDR2 range of the Californian the 2 GB Kit and make more because nowadays no peculiarity. Is all the more interesting how much performance get even from memory when needed. “Micron D9Gxx (B6-x)” chips are on the modules.
So was the memory at 800 MHz without voltage increase with timings of 4-4-3-12 run, was to move but also by increasing no longer to a further reduction in at the same time stable operation. Regarding the memory voltage we limited ourselves to an increase to 2,15V, which we after all 1008 MHz reached at CL5 timings – a clock increase of over 25%!
< div >
| Memory clock | RAM divider | FSB clock (CPU clock) | Timings | Voltage |
|---|---|---|---|---|
| 800 | 1: 1 | 400 MHz (2.8 GHz) | 4-4-3-12 | 1,9V |
| 1001 | 2: 3 | 334 MHz (3,002 GHz) | 5-5-5-15 | 2,15V |
| 1008 | 2: 3 | 336 MHz (3,024 GHz) | 5-5-5-15 | 2,15V |
The bandwidth test under Sandra reveals the problem of the external memory controller of Intel platform: the bottleneck between Northbridge and CPU ensures that the supposed weakest configuration thanks to higher FSB clock clearly at the top can do. The effect of higher measure predominates the the poorer timing in the memory latency. The bandwidth test in ScienceMark corresponds to a result with the results in Sandra: the frontside bus is too low clocked, to exploit the high memory clock.
Sandra 2007 bandwidth float FPU
Information in megabytes per second (MB/s)
|
Sandra 2007 latency
Information in nanoseconds
|
ScienceMark 2.0 bandwidth
Information in megabytes per second (MB/s)
|
Corsair DDR2-1066
Significantly higher clock rates promise Corsairs DDR2-1066 modules with CL5 timings, they are higher clocked but front away effectively 266 MHz. Along with a go but with v (due to a BIOS limitation we could test only with 2,25V) significantly higher memory voltage and not to expect a higher price. The tested modules there is a 1 GB Kit, that is available with double-capacity. On the modules, “Micron D9GMH (B6-3)” are chips installed.
Heruntergetaktet on 800 MHz we could elicit CL3 timings the modules in standard tension. This would not justify the price of the modules, but they are ultimately not be provided for. At default clock timings without voltage increase could be after all reduce to 4-4-5-12. To determine the maximum clock, we had to select the setting of the timings of the SPD, came but then at Typ. tension on a remarkable effective clock rate of 1217 MHz – good 14 percent above the plant information.
< div >
| Memory clock | RAM divider | FSB clock (CPU clock) | Timings | Voltage |
|---|---|---|---|---|
| 800 | 1: 1 | 400 MHz (2.8 GHz) | 3-3-3-9 | 2,25V |
| 1001 | 2: 3 | 334 MHz (3,002 GHz) | 4-4-3-12 | 2,25V |
| 1066 | 2: 3 | 355 MHz (2,842 GHz) | 4-4-5-12 | 2,3V |
| 1217 | 2: 3 | 406 MHz (3,245 GHz) | 5-5-5-18 | 2,3V |
The timed 355 MHz frontside bus at 1066 MHz memory clock obviously already sufficient to greatly reduce the influence of sheathing and to achieve a higher value than 400 FSB-MHz and 800 MHz memory clock. The runaway of the memory latency at 800 MHz is somewhat surprising. An explanation for the unusual values we could not find, have seen but with identical timing already test the Dominator modules the phenomenon. Problems with CL3 timings are however not new at Intel and encountered already earlier chipsets (see comparison with nVidia nForce 4 SLI (Intel Edition)).
Sandra 2007 bandwidth float FPU
Information in megabytes per second (MB/s)
|
Sandra 2007 latency
Information in nanoseconds
|
ScienceMark 2.0 bandwidth
Information in megabytes per second (MB/s)
|
OCZ DDR2-1000
OCZ sends a 2 GB Kit with promising name in the race with the OCZ DDR2 PC2-8000 Platinum extreme Edition XTC, our expectations of the overclocking of the precious modules were correspondingly high. They are specified for 1000 MHz effective clock with timings of 4-5-4-15 and v memory voltage. The latter can be within a framework guarantee demand on increased up to 2,35V. On our modules, “Micron D9GKX (B6-25E)” chips are used. In the trade “Micron D9GMH (B6-3)” are however can be found. What chips are finally really can find OCZ modules only by the removal of Heatspreaders, there is no useful information to review unfortunately.
At 800 MHz, the OCZ modules achieve very good timings of 3-4-3-9 with a memory voltage lowered to 2,1V. The first – if not really important also for the performance – we have experienced disappointment when trying to reduce the timings at 1001 MHz – even with increased memory voltage is not more than one to achieve reduction of the tRAS value from 15 to 12. The maximum frequency, reached the modules on our test system is still disappointing: already at 1015 MHz it reaches the end of the flagpole. That the timings here remain unchanged, is little comforting in the face of a Übertaktungspotenzials by just 1.5%.
< div >
| Memory clock | RAM divider | FSB clock (CPU clock) | Timings | Voltage |
|---|---|---|---|---|
| 800 | 1: 1 | 400 MHz (2.8 GHz) | 3-4-3-9 | 2,1V |
| 1001 | 2: 3 | 334 MHz (3,002 GHz) | 4-5-4-12 | 2,25V |
| 1015 | 2: 3 | 338 MHz (3,046 GHz) | 4-5-4-12 | 2,3V |
Familiar picture from the bandwidth test: the bottleneck between CPU and Northbridge slows down from the store. The expected image is reflected in the memory latency, the time is more important than the timing.
Sandra 2007 bandwidth float FPU
Information in megabytes per second (MB/s)
|
Sandra 2007 latency
Information in nanoseconds
|
ScienceMark 2.0 bandwidth
Information in megabytes per second (MB/s)
|
Conclusion
Corsair and OCZ competed with three very different in their key data module pairs to the test. The clear winner in the categories of Übertaktungspotential and price/performance is Corsairs TWIN2X2048-6400, which easily stepping a good underlying 25% above the factory specifications of 800 MHz clock and burdened also the wallet not unduly with a price of currently about 160 euros.
A pair of engine from the House of Corsair reached the highest clock 1217 MHz also and also the Übertaktungspotential was still very high despite a high memory clock as the starting point with 14%. Less encouragingly, most buyers are likely to find the estimated price: currently 198 euros for the 1-GB Kit we tested or 310 euro for the 2 GB kit should not are worthwhile for most buyers, Übertakter are likely to have on the modules, but their joy.
The clear loser in the test box is the OCZ DDR2 PC2-8000 Platinum extreme Edition XTC baptized kit of OCZ. At prices which present to 440 euros (the only retailer, which lists the modules currently in stock, required even exorbitant 554 euros) can start and a not too high guaranteed clock 1000 MHz only 1.5% not really convince overclocking. Fair way should be mentioned however, that much better cut the modules in other tests, and we have received perhaps only a ungwöhnlich bad module pair. Also the interaction between the test system and memory should forget at this point as a possible cause.
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