Nehalem is Intel’s processor family of the next generation, which makes hearts beat: the memory controller moves as AMD finally into the processor, the frontside bus is retired and HyperThreading comes back under a different name. Also the other innovations can see themselves.

Now also a chipset for the completely modified infrastructure celebrates with Tylersburg be matching the patterns (engineering samples) planned for October 2007 and the speculation to a triple-channel memory interface Tapeout – first prototype can thus produced and begin a long validation and testing. To test there are doing enough, not least because it is the first product, where the frontside bus replaced with QuickPath (codename CSI), a fast point to point data link.

Tylersburg is as Northbridge of the “Thurley” platform for systems with two processor sockets (Xeon DP family, new name for the segment: efficient performance (EP)) designed, but equally comes equipped with a socket Xeon platform “Foxhollow” (new segment name: entry (EN)) to use and runs also with the extreme Edition processor in the desktop area (high-end desktop, HEDT) as part of the Kings Creek platform (hopefully) to top form on.

In detail, it is still little known about Tylersburg. It is clear that the Northbrige on the “Thurley” platform with the quad-core processor Gainestown and on the “Foxhollow”- and is combined with Bloomfield, also a quad-core chip Nehalem-based on the “Thurley” platform. What CPU socket used coming, it is not clear; so far, the rumor mill has only socket B (LGA1366) and socket H (LGA715). The chances are not bad that Intel for HEDT uniformly sets up EP on the better version. Thus it facilitates the upgrade to a system with two processors all enthusiasts and more to the far more expensive “extreme editions” be distinguished from the mass-produced. Intel’s response to AMD’s QuadFX (4 x 4), the Skulltrail chipset expected at the end, is perhaps but not a fluke and is maintained in the future such as QuadFX.

Tylersburg is produced as the first workstation/server chipset in the P1265 production process (65 nm) to 2008 are used at all (Northbridge) chipsets. After a development time of almost two years, the completed A0 stepping Intel’s apparently exceeded expectations in terms of performance and power consumption. Compared with the Seaburg chip set expected at the end of (EP Stoakley platform) of the power consumption should have halved. The number of PCI Express lanes (Gen 2) is to compared to the 32 lanes of Seaburg (plus the Gen 1 of the southbridge) have increased.

Nehalem and its complete platform evolve so magnificently and finally approach the completion. The whole project GHz processor clock is designed in the context of the gigahertz race originally for end of 2005 as a single-core chip with over 10 and had to be redesigned with the paradigm shift towards performance/watt completely. Nehalem to appear in the second half of next year.

“Intel Nehalem-generation overview” Photo Gallery (17 images)